Pull-Up Resistors - Intel PXA27 Series Design Manual

JTAG Debug
The tasks of a pulse or DC level nTRST reset are:
•
Selection of the system mode (the boundary-scan chain does not intercept the signals that pass
between the pads and the core).
•
Selection of the idcode instruction. If TCK is pulsed, the contents of the ID register are
clocked out of TDO.
If JTAG is not used, at a minimum, the nTRST signal must be connected to the nRESET signal to
cause a reset on nTRST at power-up. TCK must be grounded.
Refer to the ARM* Multi-ICE System Design Considerations, Application Note 72 (ARM DAI
0072A) for additional information on the JTAG interface.
26.4.2

Pull-Up Resistors

The IEEE 1149.1 standard effectively requires that TDI, TMS, and nTRST have internal pull-up
resistors. Leave the TDI and TMS pins left unconnected when not in use. TCK must be tied low in
cases where JTAG is not used.
Scan Chain
PXA27x has 4 scan chains, controlled from a single JTAG style TAP controller. These are referred
to as scan chains 0,1, 2, and 3 and are arranged as shown in
Arrangement". The scan chains are selected by a TAP controller instruction.
Scan Chain
0 This allows access to the PXA27x core. The scan chain's functions allow inter-macrocell
testing (EXTEST), and allow the core's test patterns to be applied serially (INTEST). The
order of the scan chain (from TDI to TDO) sequentially:
1. Data bus bits 0 through 3
2. Control signals (order to be determined)
3. Address bus bits 31 through 0
1 This is a small scan chain which only allows access to the core's data bus. There are 32 scan
cells in this chain. This scan chain is used during debug to insert instructions into the
processor's pipeline and capture the internal state as it is written. The order of the scan chain
is (from TDI to TDO): data bus bits 0 through 31.
2 This is a scan chain around the PXA27x ICEbreaker macrocell. This allows the watchpoint
registers to be programmed and tested.
3 This is a scan chain around the whole of the PXA27x. The scan chain allows the PXA27x
core to be exercised (INTEST) and allows inter-device testing at a board level (EXTEST).
The order of the scan chain is to be determined.
II:26-4
Figure 26-2, "PXA27x Scan Chain
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Intel PXA27x Processor Family Design Guide