Block Diagram; Layout Notes - Intel PXA27 Series Design Manual

14.3

Block Diagram

See Figure 14-1
2
Figure 14-1. I S Controller Interface Block Diagram
Processor
2
I S Controller
14.4

Layout Notes

It is important to follow proper mixed-signal layout procedures because of the analog/digital nature
of the CODEC. Refer to the layout recommendations provided in the CODEC data sheet. Some
general recommendations are:
•
Use a separate power supply for the analog audio portion of the design.
•
Place a digital power/ground plane keep-out underneath the analog portion. Use a separate
analog ground plane. Create an island inside the keep-out. Connect the digital ground pins of
the CODEC to the digital ground. Keep the two ground planes on the same layer, with at least
0.125 inches (3.135 mm) separation between the ground planes.
Connect the two ground planes underneath the CODEC with a 0 Ω jumper. Add optional Do-
•
Not-Populate populate 0 Ω jumpers between analog and digital ground at the power supply.
Reduce excessive noise on the board by installing the 0 Ω resistor.
•
Do not route digital signals underneath the analog portion. Ensure the digital traces go over the
digital ground plane and analog traces go over the analog plane.
•
Buffer any digital signals to or from the CODEC that go off the board (for example, if the
CODEC is on a daughter card).
•
Fill the areas between analog traces with copper tied to the analog ground. Fill the regions
between digital traces with copper tied to the digital ground.
•
Locate the decoupling capacitors for the analog portion as close to the CODEC as possible.
®
Intel PXA27x Processor Family Design Guide
for the PXA27x processor I
PXA27x
SYSCLK
BITCLK
SYNC
SDATA_OUT
SDATA_IN
PXA27x processor supports L3
Bus protocol using software
control of GPIO signals; no
hardware control for L3 Bus
2
S controller interface block diagram.
2
I S Interface
2
I S Codec
CLOCK
BITCLK
SYNC
DAC_DATA
ADC_DATA
Optional L3 Bus Control
Signals (L3_CLK,
L3_DATA, & L3_MODE)
I2S_001_P2
II:14-3