Modes Of Operation; Fly-By Dma Transfers; Signals; Fly-By Dma Transfer Signals - Intel PXA27 Series Design Manual

5.5

Modes of Operation

The following subsections describe the procedures for interfacing with the PXA27x processor
DMA controller and memory controller when using either fly-by or flow-through DMA transfers.
5.5.1

Fly-By DMA Transfers

Fly-by transfers must occur only between any SDRAM partition and external peripherals or
companion chips.
5.5.1.1

Signals

See Table 5-2
by DMA transfer capabilities.
Table 5-2. Fly-By DMA Transfer Signals
Signal Name
DREQ<1:0>
DVAL<1:0>
®
Intel PXA27x Processor Family Design Guide
for the list of signals required for interfacing with the PXA27x processor using fly-
Type
External Companion Chip Request
The DMA controller detects the positive edge of DREQ
signal to log a request. The external companion chip
Input asserts the DREQ signal when a DMA transfer request is
required.
Requests on pins DREQ<1:0> are used for data transfers
in fly-by mode.
External Companion Chip Valid
Output
The memory controller asserts DVAL to notify the
companion chip that data must be driven or is valid.
DMA Controller Interface
Description
II:5-3