Interrupt Interface; Overview - Intel PXA27 Series Design Manual

Interrupt Interface

This chapter describes the procedures for interfacing with the interrupt controller of Intel
PXA27x Processor Family (PXA27x processor).
25.1

Overview

The interrupt controller interfaces to both internal and external peripheral interrupt request. The
means of interfacing an external peripheral interrupt request is through the GPIO signals. All the
GPIO signals are configured to generate an interrupt on a rising edge, falling edge or both edges.
Refer to the Interrupt and GPIO sections in the Intel
Manual for enabling interrupts through GPIO signals and for setting the edge of the appropriate
GPIO interrupt.
To configure the GPIO<120:0> signals as interrupt signals, perform these steps:
1. Program the GPIO pin direction using the GPDRx register.
2. Program the GPIO edge detect using the GRERx or GFERx registers.
3. Program the GPIO alternate function using the GAFRx_x register.
4. Determine if the GPIO interrupt generates an IRQ or FIQ interrupt using the ICLR register.
5. Configure the priority of the GPIO interrupt using the IPR8
6. Unmask the GPIO interrupts using the ICMR<10:8> register.
Note: GPIO<120:119> are only available in the Intel
All references to registers are documented in the Intel
Manual unless otherwise noted.
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Intel PXA27x Processor Family Design Guide
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PXA27x Processor Family Developers
IPR10 registers.
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PXA27x Processor Family.
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PXA27x Processor Family Developers
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