Intel PXA27 Series Design Manual page 9

19 USIM Controller Interface ....................................................................................................II: 19-1
19.1 Overview ......................................................................................................................II: 19-1
19.2 Signals .........................................................................................................................II: 19-2
19.2.1 PXA27x Processor USIM Interface Signals ....................................................II: 19-2
19.2.2 USIM Card Interface Signals ..........................................................................II: 19-3
19.3 Block Diagram .............................................................................................................II: 19-4
19.4 Layout Notes................................................................................................................II: 19-5
20 Universal Serial Bus Host Interface....................................................................................II: 20-1
20.1 Overview ......................................................................................................................II: 20-1
20.2 Signals .........................................................................................................................II: 20-1
20.3 Block Diagrams............................................................................................................II: 20-2
20.3.1 Block Diagram for USB Host Differential Connection (Port 1 or Port 2) .........II: 20-2
20.3.2 Block Diagrams for USB Host Port 2 (Differential or Single-Ended)...............II: 20-3
20.3.3 Block Diagram for USB Host Single-Ended Connection (Port 3)....................II: 20-4
20.4 Layout Notes................................................................................................................II: 20-5
21 Real Time Clock Interface....................................................................................................II: 21-1
21.1 Overview ......................................................................................................................II: 21-1
21.2 Signals .........................................................................................................................II: 21-1
21.3 Block Diagram .............................................................................................................II: 21-2
21.4 Layout Notes................................................................................................................II: 21-2
22 OS Timer Interface................................................................................................................II: 22-1
22.1 Overview ......................................................................................................................II: 22-1
22.2 Signals .........................................................................................................................II: 22-1
22.3 Block Diagram .............................................................................................................II: 22-2
22.3.1 Channel Access/Control Block .......................................................................II: 22-2
22.3.2 PXA25x Compatibility Channels 0-3 Block .....................................................II: 22-2
22.3.3 Channels 4 - 11 Blocks ...................................................................................II: 22-3
22.3.4 Output Control ................................................................................................II: 22-3
22.4 Layout Notes................................................................................................................II: 22-3
23 Pulse-Width Modulator Interface ........................................................................................II: 23-1
23.1 Overview ......................................................................................................................II: 23-1
23.2 Signals .........................................................................................................................II: 23-1
23.3 Block Diagram .............................................................................................................II: 23-2
23.4 Layout Notes................................................................................................................II: 23-2
24 General Purpose Input/Output Interfaces ..........................................................................II: 24-1
24.1 Overview ......................................................................................................................II: 24-1
24.2 Signals .........................................................................................................................II: 24-1
24.3 Block Diagram/Schematic............................................................................................II: 24-3
24.4 Layout Notes................................................................................................................II: 24-3
25 Interrupt Interface.................................................................................................................II: 25-1
25.1 Overview ......................................................................................................................II: 25-1
25.2 Signals .........................................................................................................................II: 25-2
25.3 Block Diagram .............................................................................................................II: 25-3
25.4 Layout Notes................................................................................................................II: 25-4
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Intel PXA27x Processor Family Design Guide
Contents
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