Vlio Block Diagram; Vlio Memory Layout Notes; Pc Card (Pcmcia) Interface; Variable Latency Interface Block Diagram - Intel PXA27 Series Design Manual

6.5.5.2

VLIO Block Diagram

See Figure 6-9
processor using the VLIO memory interface.
Figure 6-9. Variable Latency Interface Block Diagram
6.5.5.3

VLIO Memory Layout Notes

Refer to Section 6.4
®
Intel PXA270 Processor Electrical, Mechanical, and Thermal Specification and Intel
Processor Family Electrical, Mechanical, and Thermal Specification for AC timing information.
6.5.6

PC Card (PCMCIA) Interface

The PXA27x processor requires external glue logic to complete the 16-bit PC Card socket interface
that allows either 1-socket or 2-socket solutions.
The following illustrations show general solutions for a one- and two-socket configurations:
•
Figure 6-10, "External Logic for a One-Socket Configuration Expansion PC Card," on page II:
6-27
•
Figure 6-11, "External Logic for a Two-Socket Configuration Expansion PC Card," on
page II: 6-28
The pull-ups shown are included as specified in the PC Card Standard, Volume 2, Electrical
Specification, PCMCIA/JEITA. Low-power systems must remove power from the pull-ups during
sleep to avoid unnecessary power consumption.
GPIO or memory-mapped external registers controls the reset of the 16-bit PC Card interface,
power selection (VCC and VPP), and drive enables. The INPACK# signal is not used.
®
Intel PXA27x Processor Design Guide
for illustration of the signals when connecting a companion chip to the PXA27x
PXA27x
PXA27x
Memory
Controller
for recommendation on trace lengths, size, and routing guidelines. Refer to
System Memory Interface
EXTERNAL SYSTEM
nCSx
nOE
nPWE
MA<25:0>
DQM<3:0>
MD<31:0>
RDY
Companion
Chip
®
PXA27x
II:6-23