Trace Space To Trace Width Ratio; Common Clock Signals; Figure 4. Trace Spacing Vs. Trace To Reference Plane Example; Figure 5. Three To One Trace Spacing To Trace Width Example - Intel 855GM Design Manual

Intel Pentium M/Celeron M Front Side Bus Design Guidelines

Figure 4. Trace Spacing vs. Trace to Reference Plane Example

4.1.1.2.

Trace Space to Trace Width Ratio

Figure 5 illustrates the recommended relationship between the edge-to-edge trace spacing versus trace
width ratio for the best signal quality results. In general, a 3:1 trace space to trace width ratio is preferred
and highly recommended. In case of routing difficulties on the motherboard, using a 2:1 ratio would be
acceptable only if additional simulations conclude that it is possible, which may include some changes
to the stack-up or routing assumptions.

Figure 5. Three to One Trace Spacing to Trace Width Example

4.1.2.

Common Clock Signals

All common clock signals use an AGTL+ bus driver technology with on die integrated GTL termination
resistors connected in a point-to-point, Zo = 55 Ω, controlled impedance topology between the processor
and the GMCH. No external termination is needed on these signals. These signals operate at the PSB
frequency of 100 MHz.
Common clock signals should be routed on an internal layer while referencing solid ground planes.
Based on current simulation results, routing on internal layers allows for a minimum pin-to-pin
motherboard length of approximately 1.0 inch and a maximum of 6.5 inches. Trace length matching for
the common clock signals is not required. For details on minimum motherboard trace length
requirements, please refer to Section 4.1.2.1 and Table 2 for more details. Intel recommends routing
these signals on the same internal layer for the entire length of the bus. If routing constraints require
routing of these signals with a transition to a different layer, a minimum of one ground stitching via for
every two signals should be placed within 100 mils of the signal transition vias.
Routing of the common clock signals should use 2:1 trace spacing to trace width. This implies a
minimum of 8 mils spacing (i.e. 12-mil minimum pitch) for a 4-mil trace width for routing on internal
layers. Practical cases of escape routing under the GMCH or processor package outline and vicinity may
not allow the implementation of 2:1 trace spacing requirements. Although every attempt should be made
to maximize the signal spacing in these areas, it is allowable to have 1:1 trace spacing underneath the
GMCH and the processor package outlines and up to 200 – 300 mils outside the package outline.
38
R e fe r e n c e P la n e ( V S S )
T r a c e
T r a c e
2 X
3 X
v
®
Intel 855GM/855GME Chipset Platform Design Guide
X
T r a c e
T r a c e
X
v
R