The Event Machines; The Debug Registers - Intel l2ICE User Manual

An arm specification specifies both a breakpoint and an arm window. The arm window deter­
mines when the PICE system can recognize the breakpoint. (For more information on what
kinds of arm specification conditions can be selected, see the GO entry in the PICE™ System
Reference Manual.) For example, the following command opens the arm window only when
the procedure payment is executing. If the program variable quarters is read and the arm
window is open, a break occurs.
*GO TIL ARM :ctnakenpayinent
* *DISARM OUTSIDE icirtaker.paymeni
* *TRKS READ AT ,:cmakenquarter$

The Event Machines

The PICE system contains two event machines: the execution event machine (XEM) and the
system event machine (SEM). When you set breakpoint, trace, and arm specifications, you are
programming one or both of these event machines.
An execution event is the execution of an instruction. You specify an execution event as an
address or range of addresses. The execution event occurs when the microprocessor is ready to
execute the instruction that came from the address or address range. Execution begins when
the first byte of the instruction is taken from the instruction queue.
A system event describes activity on the microprocessor address lines, the microprocessor data
lines, the microprocessor status lines, or the clips input lines. The PICE system can read the
state of the clips input lines and break, trace, or arm on their values.
You can program the event machines directly if you need to specify a complex event. Each
event machine has four states (SO through S3). Each state represents a control branch that can
detect match conditions (e.g., break or trace), initiate actions, or branch to a new state. State
S3 sets up a communication link between the two event machines so that decisions can be made
in one machine based on the condition of the other.
In addition, each event machine has a counter that you can set and conditionally increment.
Then, you can change the event machine's state if the counter is equal to the set value. (For
more information on the event machines, see the Event machines entry in the PICE™ System
Reference Manual.)

The Debug Registers

A debug register is a software register that you create and name with an PICE command. The
five types of debug registers are arm (ARMREG), break (BRKREG), system (SYSREG),
trace (TRCREG), and event (EVTREG). You can define any number of each type, edit them,
emulate with them, and write them to a disk file for later debug sessions. (Detailed information
on each register type is given in the corresponding entry in the PICE™ System Reference
Manual.)
Introduction to Using the PICE™ System
3-35