ABB RET650 Technical Manual page 255

1MRK 504 135-UEN A
Technical manual
DUDI Detection
DUDI detection Phase 1
IL1
DI<
UL1
DU>
a
b
UPh>
IL2
DUDI detection Phase 2
UL2
IL3
DUDI detection Phase 3
UL3
UL1
a
a<b
b
IL1
a
a>b
b
IPh>
CBCLOSED
UL2
a
a<b
b
IL2
a
a>b
b
UL3
a
a<b
b
IL3
a
a>b
b
IEC10000034 V1 EN
Figure 112: Simplified logic diagram for DU/DI detection part
Secondary system supervision
One cycle
delay
|DI|
One cycle
delay
|DU|
20 ms 1.5 cycle
a>b
t
t
Same logic as for phase 1
Same logic as for phase 1
AND
OR
AND OR
AND
OR
AND
OR
AND
OR
AND
OR
Section 11
a
a>b
b
a
a>b
AND
b
AND
AND
AND
FuseFailDetDUDI
OR
IEC10000034-1-en.vsd
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