Port 3 Registers (Pdr3, Ddr3) - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 4 I/O PORTS
4.5.1

Port 3 Registers (PDR3, DDR3)

This section describes the port 3 registers.
Port 3 Register Functions
Port 3 data register (PDR3)
The PDR3 register holds the states of pins. From the bit corresponding to a pin set as an output
port pin, therefore, the same value ("0" or "1") as the output latch can be read. From the bit
corresponding to a pin set as an input port pin, the output latch value cannot be read but the pin
state is read instead.
Tip:
Since the bit manipulation instructions (SETB and CLRB) do not read pin values but output
latch values, they do not change the output latch values other than those in the bits they
manipulate.
Port 3 data direction register (DDR3)
The DDR3 register sets the direction (input or output) for each pin (bit).
Setting "1" to the bit corresponding to a port (pin) sets the pin as an output port. Setting "0" sets
the pin as an input port.
Check:
As the DDR3 register is write-only, the bit manipulation instructions (SETB and CLRB)
cannot be used.
Setting for peripheral output
To use a peripheral having output pins, enable the output enable bit for the peripheral.
Since the peripheral output is handled preferentially, the PDR3 and DDR3 register values set for
the peripheral output pin are meaningless, regardless of the peripheral output value and output
enable/disable status.
Setting for peripheral input
To use a peripheral having input pins, set the input pin of the peripheral as an input port pin.
The corresponding output latch value is meaningless at this time.
120