Notes On Using Watchdog Timer - Fujitsu F2MC-8L Series Hardware Manual

6.5

Notes on Using Watchdog Timer

This section lists points to note when using the watchdog timer.
Notes on Using Watchdog Timer
Stopping watchdog timer
Once activated, the watchdog timer can not stop until a reset generates.
Selecting the count clock
The count clock select bit (WDTC: CS) can be updated only when the watchdog timer control
bits (WDTC: WTE3 to WTE0) are set to "0101
manipulation instructions cannot therefore be used to write to the count clock select bit. Once
the watchdog timer has been activated, do not change the setting.
In subclock mode, the main clock stops oscillation and thus the timebase timer does not
operate.
The watch prescaler must be selected as the count clock (WDTC: CS = "1") before the
watchdog timer can operate in subclock mode.
Clearing watchdog timer
• Clearing the counter (timebase timer or watch prescaler) used for watchdog timer count
clock also simultaneously clears the watchdog timer counter.
• The watchdog timer counter is cleared on changing to sleep mode, stop mode, or watch
mode.
Notes on programming
When writing a program in which the watchdog timer is repeatedly cleared in the main loop,
ensure that the processing time for the main loop, including interrupt processing, is less than the
minimum watchdog timer interval time.
Operation in subclock mode
If a watchdog reset occurs in subclock mode, the watchdog timer starts operation in main clock
mode after the oscillation stabilization delay time has passed. When the reset output option has
been selected, therefore, the reset signal remains output until the end of the oscillation
stabilization delay time.
6.5 Notes on Using Watchdog Timer
" upon activation of the watchdog timer. Bit
B
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