Timer 2 Data Register (T2Dr); Figure 7.4-5 Timer 2 Data Register (T2Dr) - Fujitsu F2MC-8L Series Hardware Manual

7.4.4

Timer 2 Data Register (T2DR)

The timer 2 data register (T2DR) is used to set the interval timer value (for the interval
timer function) or counter value (for the counter function) either for timer 2 in 8-bit
mode or for the upper eight bits of the 16-bit timer. The T1DR register is also used to
read the counter value.
Timer 2 Data Register (T2DR)
The value set in this register is compared to the counter value. When this register is read, it
returns the counter value. The value set in the register cannot be read.
Figure 7.4-5 shows the bit structure of the timer 2 data register.
Address
001A
R/W : Readable and writable
X : Indeterminate
In 8-bit mode (Timer 2)
The value in the T2DR register is compared to the counter value. The register sets the interval
time value when the interval timer function is used; it sets the count to be detected when the
counter function is used. The T2DR register value is reset in (loaded to) the comparate data
latch at the start of counting or upon detection of a match with the counter value.
If a value is written to the T2DR register during operation of the counter, the value is made valid
in the next cycle (after detection of a match).
Tip:
The value set in the T2DR register during operation of the interval timer is calculated from
the equation below. Note, however, that the instruction cycle depends on the clock mode
and gear function.
In 16-bit mode
The value in the T2DR register is compared to the counter value in the upper eight bits of the
16-bit timer. The register sets the upper eight bits of the interval time when the interval timer
function is used; it sets the upper eight bits of the count to be detected when the counter
function is used. The T2DR register value is loaded to the upper eight bits of the comparate
data latch upon start of counting and upon detection of a match with the 16-bit count value. The
value written to the T2DR register during operation of the 16-bit counter is made valid after a
match is detected. Count operation in 16-bit mode is controlled based on the timer 1 control
register (T1CR).

Figure 7.4-5 Timer 2 Data Register (T2DR)

Bit 7 Bit 6 Bit 5
H
R/W R/W R/W
T2DR register value = interval time/(count clock cycle × instruction cycle) - 1
Bit 4 Bit 3 Bit 2 Bit 1
R/W R/W R/W R/W
7.4 8/16-bit Timer/Counter Registers
Bit 0 Initial value
XXXXXXXX
B
R/W
173