12.4 Watch Prescaler Interrupts; Table 12.4-1 Register And Vector Table For Watch Prescaler Interrupt - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 12 WATCH PRESCALER

12.4 Watch Prescaler Interrupts

The watch prescaler generates an interrupt request at the rising edge of the selected
frequency-divided output (using the interval timer function).
Interrupts (Watch Interrupts) during Operation using Interval Timer Function
When the watch prescaler counter increments the count in synchronization with the subclock
source oscillation and the interval timer time has passed, the watch interrupt request flag bit
(WIF) in the WPCR register is set to "1" if the device is not in main-stop mode. If the interrupt
request enable bit has been enabled (WPCR: WIE = "1") at this point, the watch prescaler
generates an interrupt request (IRQ7) to the CPU. Use the interrupt handler to write "0" to the
WIF bit to clear the interrupt request to "0". Note that the WIF bit is set at the falling edge of the
specified frequency-divided output regardless of the value in the WIE bit.
Check:
When enabling interrupt request output (WIE = "1") after waking up the device from a reset,
be sure to clear the WIF bit (WIF = "0") at the same time.
Notes:
• An interrupt request is generated as soon as the WIE bit is enabled from disabled ("0" -->
1") when the WIF bit is "1".
• The WIF bit is not set when the counter is cleared (WPCR: WCLR = "0") at the same time as
when the selected bit overflows.
Oscillation Stabilization Delay Time and Watch Interrupts
If the set interval time is shorter than the subclock oscillation stabilization delay time, the watch
prescaler generates a watch interrupt request (WPCR WIF = 1) when an external interrupt
wakes up the device from sub-stop mode. In this case, disable watch prescaler interrupts
(WPCR: WIE = "0") when entering the sub-stop mode.
Register and Vector Table for Watch Prescaler Interrupt
Table 12.4-1 shows the register and vector table for the watch prescaler Interrupt.

Table 12.4-1 Register and Vector Table for Watch Prescaler Interrupt

Interrupt
IRQ7 ILR2 (007D
Reference:
See Section 3.4.2, "Interrupt Processing" for details on interrupt operation.
268
Interrupt level setting register
Register
) L71 (Bit 7)
H
Setting bits
L70 (Bit 6)
Vector table address
Upper Lower
FFEC FFED
H H