Fujitsu F2MC-8L Series Hardware Manual page 15

3.7.6 State Transition Diagram 1 (Product with Power-on Reset Function in Dual-clock Configuration) 83
3.7.7 State Transition Diagram 2 (Product without Power-on Reset Function in Dual-clock
Configuration) ................................................................................................................................ 86
3.7.8 State Transition Diagram 3 (Products in Single-clock Configuration) ............................................ 89
3.7.9 Pin States in Standby Modes ......................................................................................................... 91
3.7.10 Notes on Using Standby Modes .................................................................................................... 93
3.8 Memory Access Modes ....................................................................................................................... 95
CHAPTER 4 I/O PORTS .................................................................................................. 97
4.1 Overview of I/O Ports .......................................................................................................................... 98
4.2 Port 0 ................................................................................................................................................ 100
4.2.1 Port 0 Registers (PDR0, DDR0) .................................................................................................. 103
4.2.2 Operation of Port 0 ...................................................................................................................... 105
4.3 Port 1 ................................................................................................................................................ 107
4.3.1 Port 1 Registers (PDR1, DDR1) .................................................................................................. 109
4.3.2 Operation of Port 1 ...................................................................................................................... 111
4.4 Port 2 ................................................................................................................................................ 113
4.4.1 Port 2 Register (PDR2) ................................................................................................................ 115
4.4.2 Operation of Port 2 ...................................................................................................................... 116
4.5 Port 3 ................................................................................................................................................ 117
4.5.1 Port 3 Registers (PDR3, DDR3) .................................................................................................. 120
4.5.2 Operation of Port 3 ...................................................................................................................... 122
4.6 Port 4 ................................................................................................................................................ 124
4.6.1 Port 4 Register (PDR4) ................................................................................................................ 126
4.6.2 Operation of Port 4 ...................................................................................................................... 127
4.7 Program Example for I/O Ports ......................................................................................................... 128
CHAPTER 5 TIMEBASE TIMER .................................................................................... 131
5.1 Overview of Timebase Timer ............................................................................................................ 132
5.2 Structure of Timebase Timer ............................................................................................................ 134
5.3 Timebase Timer Control Register (TBTC) ........................................................................................ 136
5.4 Timebase Timer Interrupt .................................................................................................................. 138
5.5 Operation of Timebase Timer ........................................................................................................... 139
5.6 Notes on Using Timebase Timer ...................................................................................................... 141
5.7 Program Example for Timebase Timer ............................................................................................. 143
CHAPTER 6 WATCHDOG TIMER ................................................................................. 145
6.1 Overview of Watchdog Timer ............................................................................................................ 146
6.2 Structure of Watchdog Timer ............................................................................................................ 147
6.3 Watchdog Timer Control Register (WDTC) ...................................................................................... 149
6.4 Operation of Watchdog Timer ........................................................................................................... 151
6.5 Notes on Using Watchdog Timer ...................................................................................................... 153
6.6 Program Example for Watchdog Timer ............................................................................................. 154
CHAPTER 7 8/16-BIT TIMER/COUNTER ...................................................................... 157
7.1 Overview of 8/16-bit Timer/Counter .................................................................................................. 158
7.2 Structure of 8/16-bit Timer/Counter .................................................................................................. 161
7.3 8/16-bit Timer/Counter Pins .............................................................................................................. 163
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