Fujitsu F2MC-8L Series Hardware Manual page 24

TABLES
Table 1.2-1 MB89120/120A Series Product Lineup ....................................................................................... 4
Table 1.2-2 CPU and Peripheral Functions for MB89120/120A Series .......................................................... 4
Table 1.3-1 Package and Corresponding Products ........................................................................................ 6
Table 1.7-1 Pin Description ......................................................................................................................... 15
Table 1.7-2 Pin Description for External EPROM Pins (MB89PV130A only) .............................................. 16
Table 1.8-1 I/O Circuit Type ......................................................................................................................... 18
Table 3.1-1 General-purpose Register Area ................................................................................................ 28
Table 3.1-2 Vector Table ............................................................................................................................. 28
Table 3.2-1 Interrupt Level .......................................................................................................................... 35
Table 3.4-1 Interrupt Request and Interrupt Vector ..................................................................................... 40
Table 3.4-2 Interrupt Level Setting Bit and Interrupt Level .......................................................................... 42
Table 3.5-1 Reset Source ............................................................................................................................ 53
Table 3.5-2 Reset Source and Oscillation Stabilization Delay Time ............................................................ 54
Table 3.6-1 System Clock Control Register (SYCC) Bits ............................................................................ 66
Table 3.6-2 Operating States in Each Clock Mode ...................................................................................... 68
Table 3.6-3 Main clock Mode Operation Start Conditions and Oscillation Stabilization Delay Time ........... 72
Table 3.7-1 Operating States of the CPU and Peripheral Functions in Standby Mode ............................... 75
Table 3.7-2 Standby Control Register (STBC) Bits ..................................................................................... 82
Table 3.7-3 Switching to and from Clock Mode (Product with Power-on Reset Function in Dual-clock Configuration)
84
Table 3.7-4 Switching to and from Standby Mode (Product with Power-on Reset Function in Dual-clock Configuration)
84
Table 3.7-5 Switching to and from Clock Mode (Product without Power-on Reset Function in Dual-clock Configuration)
87
Table 3.7-6 Switching to and from Standby Mode (Product without Power-on Reset Function in Dual-clock Configuration)
88
Table 3.7-7 Switching to Main clock Mode Run State and Reset (Product in Single-clock Configuration) . 90
Table 3.7-8 Switching to and from Standby Mode (Product in Single-clock Configuration) ........................ 90
Table 3.7-9 Pin States in Standby Modes ................................................................................................... 91
Table 3.7-10 Low-power Consumption Mode Settings in Standby Control Register (STBC) ........................ 94
Table 3.8-1 Mode Pin Setting ...................................................................................................................... 95
Table 3.8-2 Mode Pins and Mode Data ....................................................................................................... 96
Table 4.1-1 Port Function ............................................................................................................................ 98
Table 4.1-2 Port Registers ........................................................................................................................... 99
Table 4.2-1 Port 0 Pins .............................................................................................................................. 101
Table 4.2-2 Correspondence between Pins and Registers for Port 0 ....................................................... 102
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