Fujitsu F2MC-8L Series Hardware Manual page 164

Table 5.3-1 Timebase Timer Control Register (TBTC) Bits (Continued)
Bit
TBIE:
Bit 6
Interrupt request enable bit
Bit 5
Bit 4 Unused bits
Bit 3
Bit 2 TBC1, TBC0:
Bit 1 Interval time select bits
TBR:
Bit 0 Timebase timer initialization
bit
5.3 Timebase Timer Control Register (TBTC)
This bit enables or disables an interrupt request output to the
CPU. An interrupt request is output when both this bit and
the overflow interrupt request flag bit (TBOF) are "1".
• The read value is indeterminate.
• Writing to these bits has no effect on the operation.
These bits select the cycle of the interval timer.
These bits select which bit of the timebase timer counter to
use as the interval timer bit.
Four different interval times can be selected.
This bit clears the timebase timer counter.
Writing "0" to this bit clears the counter to "000000
"1" has no effect and does not change the bit value.
Note:
The read value is always "1".
Function
". Writing
H
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