Figure 8.7-3 8-Bit Serial Input Operation - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 8 8-BIT SERIAL I/O
data (idle state).
Figure 8.7-3 shows the 8-bit serial input operation.
For MSB first
SDR
Serial
input data
Shift clock
SIOF bit
SST bit
Operation at Completion of Serial Input
The 8-bit serial I/O sets the interrupt request flag bit (SMR: SIOF = "1") and clears the serial I/O
transfer start bit (SMR: SST = "0") on the rising edge of the shift clock after the serial data of the
eighth bit is input or output.
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Figure 8.7-3 8-bit Serial Input Operation

Bit 7 Bit 6 Bit 5 Bit 4
#7 #6 #5 #4
#7 #6
0 1
Bit 3 Bit 2 Bit 1
#3 #2 #1
#5 #4 #3 #2
2 3 4 5
Automatically cleared when transfer completes.
Bit 0
SI pin
#0
#1 #0
Cleared
6 7 by program.
Interrupt request