Figure 4.5-1 Block Diagram Of Port 3 Pins (P30 To P32, P34 To P36); Figure 4.5-2 Block Diagram Of Port 3 Pins (P33, P37) - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 4 I/O PORTS
*1: The system clock output is optional on the MB89121.
*2: The remote-control transmission frequency output is available only in the MB89120A series.
Reference:
See Section 1.7, "I/O Pins and Pin Functions" for a description of the circuit type.
Block Diagram of Port 3

Figure 4.5-1 Block Diagram of Port 3 Pins (P30 to P32, P34 to P36)

PDR (Port data register)
PDR read
PDR read
(for bit manipulation instructions)
PDR write
DDR write
SPL: Pin state specification bit in the standby control register (STBC)
PDR (Port data register)
PDR read
PDR read
(for bit manipulation instructions)
PDR write
DDR write
SPL: Pin state specification bit in the standby control register (STBC)
118
From peripheral output
Output latch
DDR
(Port data direction register)
Stop or watch mode (SPL=1)

Figure 4.5-2 Block Diagram of Port 3 Pins (P33, P37)

Remotely controlled transmit
frequency output enable signal
Remotely controlled
transmit frequency
output
Output latch
DDR
(Port data direction register)
Stop or watch mode (SPL=1)
To peripheral input
From peripheral
output enable bit
Input buffer
P37only.
MB89120A only.
From peripheral
To peripheral input
output
From peripheral
output enable bit
Stop or watch mode
(SPL=1)
Input buffer
Pull-up resistor
(optional)
Approx. 50 k /5.0 V
Pch
P-ch
Pin
N-ch
Pull-up resistor
(optional)
Approx. 50 k /5.0 V
Pch
P-ch
Pin
N-ch