Figure 7.6-3 Operation Of Interval Timer Function (Timer 1) In 8-Bit Mode; Figure 7.6-4 Settings For Interval Timer Function (In 16-Bit Mode) - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 7 8/16-BIT TIMER/COUNTER
Figure 7.6-3 illustrates the operation of the interval timer function in 8-bit mode.

Figure 7.6-3 Operation of Interval Timer Function (Timer 1) in 8-bit Mode

Counter value
Counter cleared*
T1STR bit
(T1STP = "0")
*1: The value written to the data register during operation of the counter is made valid in the next cycle.
*2: Upon activation of the counter or detection of a match, the counter is cleared and the data register value is loaded
to the comparate data latch.
In 16-bit mode
Figure 7.6-4 illustrates the settings required to use the interval timer function in 16-bit mode.

Figure 7.6-4 Settings for Interval Timer Function (in 16-bit Mode)

Although the timer in 16-bit mode is controlled based on the timer 1 control register (T1CR), the
timer 2 control register (T2CR) must be initialized. The value set in the data registers is 16 bits
long, with the upper eight bits in the T2DR register and the lower eight bits in the T1DR register.
The 16-bit data register value is compared to the 16-bit counter value. Clearing the counter
applies to all of the 16 bits at the same time. Other operations in 16-bit mode are the same as
those of timer 1 in 8-bit mode.
178
Compared value
(E0 )
H
FF
H
E0
H
80
H
00
H
Change of T1DR value
(E0 ® FF )* 1
H H
T1DR value
(E0H)
T1IF bit
Activate
2
TO pin
Bit 7 Bit 6 Bit 5
T1CR T1IF T1IE T1OS1 T1OS0 T1CS1 T1CS0 T1STP T1STR
Bit 7 Bit 6 Bit 5
T2CR T2IF T2IE T2OS1 T2OS0 T2CS1 T2CS0 T2STP T2STR
× ×
T1DR Lower 8 bits of interval time set
T2DR Upper 8 bits of interval time set
Compared value (FF
Cleared by the program
Match
Match
Bit 4 Bit 3 Bit 2
Other than 11
Bit 4 Bit 3 Bit 2
0 0 1 1
)
H
Time
Match
Bit 1 Bit 0
Bit 1 Bit 0
× ×
: Used bit
× : Unused bit
1:Set to 1
0 : Set "0".