Figure 3.2-3 Change Of Carry Flag By Shift Instruction - Fujitsu F2MC-8L Series Hardware Manual

Cleared to "0" otherwise. Set to the shift-out value in case of a shift instruction.
Figure 3.2-3 shows the change of the carry flag by a shift instruction.
• Left shift (ROLC)
Bit 7
C
Check:
The condition code register is part of the program status (PS) and cannot be accessed
independently.
Note:
In practice, the flag bits are rarely fetched and used directly. Instead, the bits are used
indirectly by instructions such as branch instructions (such as BNZ) or the decimal
adjustment instructions (DAA, DAS). The initial value of the flags after a reset is
indeterminate.
Interrupt Acceptance Control Bit
Interrupt enable flag (I)
Interrupt is enabled when this flag is set to "1" and the CPU accepts interrupt. Interrupt is
prohibited when this flag is set to "0" and the CPU does not accept interrupt.
The initial value after a reset is "0".
Normal practice is to set the flag to "1" by the SETI instruction and clear to "0" by the CLRI
instruction.
Interrupt level bits (IL1, IL0)
These bits indicate the level of the interrupt currently being accepted by the CPU. The value is
compared with the values of the interrupt level setting registers (ILR1 to ILR3) which have a
setting for each peripheral function interrupt request (IRQ0 to IRQB).
Given that the interrupt enable flag is enabled (I = "1"), the CPU only performs interrupt
processing for interrupt requests with an interrupt level value that is less than the value of these
bits. Table 3.2-1 lists the interrupt level priorities. The initial value after a reset is "11".
Table 3.2-1 Interrupt Level
IL1
0
0
1
1

Figure 3.2-3 Change of Carry Flag by Shift Instruction

IL0
0
1
0
1
• Right shift (RORC)
Bit 0 Bit 7
Interrupt level
1
2
3
3.2 Dedicated Registers
Bit 0
C
High-low
High
Low (no interrupt)
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