12.2 Structure Of Watch Prescaler; Figure 12.2-1 Block Diagram Of Watch Prescaler - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 12 WATCH PRESCALER

12.2 Structure of Watch Prescaler

The watch prescaler consists of the following four blocks:
• Watch prescaler counter
• Counter clear circuit
• Interval timer selector
• Watch prescaler control register (WPCR)
Block Diagram of Watch Prescaler
Watch prescaler
counter
0
F
2 1 2
CL
Watch
interrupt
IRQ7
F Subclock oscillation
CL:
The values enclosed in ( ) assume operation at a subclock oscillation frequency of 32.768 kHz.
Watch prescaler counter
The watch prescaler counter is a 15-bit up-counter using subclock oscillation as the count clock.
Counter clear circuit
The counter clear circuit clears the counter at transition to sub-stop mode (STBC: STP = "1") or
at a power-on reset (optional), as well as depending on the setting (WCLR = "0") in the WPCR
register.
Interval timer selector
The interval timer selector is the circuit for selecting one of four different frequency-divided
output of the watch prescaler counter for use with the interval timer. The falling edge of the
selected frequency-divided output is used as the watch prescaler interrupt source.
264

Figure 12.2-1 Block Diagram of Watch Prescaler

1 2 3 4 5 6
2 2 3 2 4 2 5 2 6 2 7
Interval timer
selector
WIF WIE
Watch prescaler control register (WPCR)
To buzzer output
7 8 9 10 11 12 13 14
2 8 2 9 2 10 2 11 2 12 2 13
(31.25 ms)
(0.25 s)
(0.5 s)
WS1 WS0 WCLR
To watchdog timer
2 14 2 15
Clear watchdog timer
To oscillation stabilization
delay time selector of
clock controller
(1.0 s)
Power-on reset
Counter clear
circuit
Start stop mode
(in subclock mode)