3.7.8
State Transition Diagram 3 (Products in Single-clock
Configuration)
This section provides the state transition diagram for the product with the power-on
reset function and that for the product without the power-on reset function, both in the
single-clock configuration. When either type of product is used in the single-clock
configuration, the CPU has neither the subclock mode nor watch mode.
State Transition Diagram 3 (Products in Single-clock Configuration)
Figure 3.7-4 State Transition Diagram 3 (Product with Power-on Reset Function)
Figure 3.7-5 State Transition Diagram 3 (Product without Power-on Reset Function)
Power on
Power-on reset
[1]
Oscillation
stabilization delay
reset state
(7)
(4)
Main-stop state
(5)
(8)
Main clock
oscillation
stabilization delay
(7)
(4)
Main-stop state
(8)
(5)
Main clock
oscillation
stabilization delay
3.7 Standby Modes (Low-power Consumption)
Reset state
(3)
[2]
[3]
Main clock mode
(1)
Main-RUN state
Main-sleep state
(2)
(6)
Power on
[1] Externel reset
Reset state
(3)
[2]
[3]
Main clock mode
(1)
Main-RUN state
Main-sleep state
(2)
(6)
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