Overview Of Timebase Timer; Table 5.1-1 Timebase Timer Interval Time; Table 5.1-2 Clock Supplied By Timebase Timer - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 5 TIMEBASE TIMER
5.1

Overview of Timebase Timer

The timebase timer uses a 21-bit free-run counter which counts-up in sync with the
internal count clock (divide-by-two main clock source oscillation). The timebase timer
provides interval timer functions. Four different interval times can be selected. The
timebase timer also provides the timer output for the oscillation stabilization delay
time and the operating clock for the watchdog and other timers.
The timebase timer stops operation in any mode in which the main clock stops
oscillation.
Interval Timer Function
The interval timer function generates repeated interrupts at fixed time intervals.
• The timer generates an interrupt each time the interval timer bit overflows on the timebase
timer counter.
• The interval timer bit (interval time) can be selected from four different settings.
Table 5.1-1 lists the available interval times for the timebase timer.

Table 5.1-1 Timebase Timer Interval Time

Internal count clock cycle
F : Main clock source oscillation
CH
Values within parentheses are values at 4.2-MHz main clock oscillation mode.
Clock Supply Function
The clock supply function provides the timer output used for the oscillation stabilization delay
time (can select one of two values as an option) and an operation clock for some peripheral
functions.
Table 5.1-2 lists the cycles of the clocks that the timebase timer supplies to various peripherals.

Table 5.1-2 Clock Supplied by Timebase Timer

Clock destination
Oscillation
stabilization delay
time
132
(0.48 µs)
2/F
CH
Clock cycle
4
2 /F (approx. 0.0 ms)
CH
12
2 /F (approx. 0.98 ms)
CH
16
2 /F (approx. 15.6 ms)
CH
18
2 /F (approx. 62.4 ms)
CH
Interval time
13
2 /F (approx. 1.95 ms)
CH
15
2 /F (approx. 7.80 ms)
CH
18
2 /F (approx. 62.4 ms)
CH
22
2 /F (approx. 998.6 ms)
CH
The clock controller selects the clock
cycle depending on the oscillation
stabilization delay time select bits
(WT1 and WT0) in the system clock
control register (SYCC).
Remarks