10.5 External Interrupt Circuit 1 Interrupts; Table 10.5-1 Register And Vector Table For External Interrupt Circuit 1 Interrupts - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)

10.5 External Interrupt Circuit 1 Interrupts

The external interrupt circuit 1 can generate interrupt requests when it detects a
specified edge on the signal input to an external interrupt pin.
Interrupts for External Interrupt Circuit 1 Operation
When a specified edge on an external interrupt input is detected, corresponding external
interrupt request flag bit (EIC1, EIC2: EIR0 to EIR2) is set to "1". At this time, an interrupt
requests (IRQ0 to IRQ2) to the CPU are generated if the corresponding interrupt request enable
bit is enabled (EIC1, EIC2: EIE0 to EIE2 = "1"). Write "0" to the corresponding external interrupt
request flag bit in the interrupt processing routine to clear the interrupt request.
Check:
When enabling interrupts (EIE0 to EIE2 = "1") after wake-up from a reset, always clear the
corresponding external interrupt request flag bit (EIR0 to EIR2 = "0") at the same time.
The device cannot recover from the interrupt processing if the external interrupt request flag
bit is "1" and the interrupt request enable bit is enabled. In the interrupt processing routine,
always clear the external interrupt request flag bit.
Tip:
• The external interrupt request flag bit is set when an edge with a matching polarity is
detected, regardless of the values in the interrupt request enable bits (EIE0 to EIE2).
• Wake-up from stop mode by an interrupt is possible using only the external interrupt circuits
1 and 2.
• An interrupt request is generated immediately if the external interrupt request flag bit is "1"
when the interrupt request enable bit is changed from disabled to enabled ("0" --> "1").
Register and Vector Table for External Interrupt Circuit 1 Interrupts

Table 10.5-1 Register and Vector Table for External Interrupt Circuit 1 Interrupts

Interrupt
IRQ0 ILR1 (007C
IRQ1 ILR1 (007C
IRQ2 ILR1 (007C
Reference:
See Section 3.4.2, "Interrupt Processing" for details on the interrupts operation.
240
Interrupt level setting register
Register
) L01 (Bit 1)
H
) L11 (Bit 2)
H
) L21 (Bit 3)
H
Setting bits
L00 (Bit 0)
L10 (Bit 2)
L20 (Bit 4)
Vector table address
Upper Lower
FFFA FFFB
H
FFF8 FFF9
H
FFF6 FFF7
H
H
H
H