11.5 External Interrupt Circuit 2 Interrupts; Table 11.5-1 Register And Vector Table For External Interrupt Circuit 2 Interrupts - Fujitsu F2MC-8L Series Hardware Manual

11.5 External Interrupt Circuit 2 Interrupts

The interrupt source of external interrupt circuit 2 is the "L" level signal input to any
external interrupt pin.
External Interrupt Circuit 2 Interrupts
When an "L" level signal is input to any external interrupt pin enabled for external interrupt input,
the external interrupt request flag bit (EIF2: IF20) is set to "1" and an interrupt request (IRQA) is
generated to the CPU. Use the interrupt handler to write "0" to the IF20 bit to clear the interrupt
request.
Once the external interrupt request flag bit (IF20) is set to "1", the interrupt request remains
generated until the IF20 bit is cleared to "0" even when external interrupt input is prohibited by
the corresponding interrupt enable bit (IE20 to IE27) in the external interrupt 2 control register
(EIE2). Therefore, be sure to clear the IF20 bit to "0".
If the external interrupt pin is left at the "L" level, even though the IF20 bit is cleared without
disabling the pin for external interrupt input, the IF20 bit is set again soon after it is cleared.
Disable the external interrupt input or remove the cause of the external interrupt itself as
required.
Check:
To enable the CPU for interrupts after waking it up from a reset, clear the IF20 bit in
advance.
Tips:
• "L" level signal inputs to external interrupt pins (INT20 to INT27) generate the same interrupt
request (IRQA). The port data register (PDR0) must therefore be read to identify the pin
corresponding to the current external interrupt input before the input changes to the "H" level.
• Waking up the CPU from stop mode by an interrupt is possible only by using external
interrupt circuit 1 or 2.
Register and Vector Table for External Interrupt Circuit 2 Interrupts

Table 11.5-1 Register and Vector Table for External Interrupt Circuit 2 Interrupts

Interrupt
IRQA
Reference:
See Section 3.4.2, "Interrupt Processing" for details on interrupt operation.
Interrupt level setting register
Register
ILR3 (007E ) LA1 (Bit 5)
H
11.5 External Interrupt Circuit 2 Interrupts
Setting bits
LA0 (Bit 4)
Vector table address
Upper Lower
FFE6 FFE7
H H
255