Fujitsu F2MC-8L Series Hardware Manual page 84

Mode Pins
The MB89120/120A series works only in the single-chip mode. Be sure to set mode pins
(MOD1, MOD0) to "Vss, Vss". The internal ROM is specified as the destination for mode data
and reset vector read out.
Do not change the mode pin settings, even after the reset has completed.
Mode Fetch
When the CPU wakes up from a reset, the CPU reads the mode data and reset vector from the
internal ROM.
Mode data (address: FFFD
For mode data, be sure to set single-chip mode (00
Reset vector (address: FFFE
Contains the address where execution is to start after completion of the reset. The CPU starts
executing instructions from the address contained.
Oscillation Stabilization Delay Reset State
On products with power-on reset, the reset operation for a power-on reset or external reset in
stop mode starts after the oscillation stabilization delay time for main clock selected by option
setting. If the CPU has not waked up from the external reset input when the delay time
completes, the reset operation does not start until the CPU wakes up from external reset.
As the oscillation stabilization delay time is also required when an external clock is used,
external clock input is required at a reset.
The main clock oscillation stabilization delay time is determined by the timebase timer.
On products without power-on reset, the oscillation stabilization delay reset state is not used.
Therefore, for such products, hold the external reset pin (RST) at the "L" level to disable the
CPU operation until the source oscillation stabilizes.
Effect of Reset on RAM Contents
An external reset is not synchronized with the internal clock. It directly turns to an internal reset.
Therefore, the contents of RAM may change before or after the reset. Initialize the RAM before
use.
)
H
(upper), FFFF (lower))
H H
).
H
3.5 Resets
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