Fujitsu F2MC-8L Series Hardware Manual page 97

CHAPTER 3 CPU
Switching from main clock mode to subclock mode
Writing "0" to the system clock select bit (SCS) in the system clock control register (SYCC)
switches the CPU from main clock mode to subclock mode.
The current operating clock can be checked by reading the system clock monitor bit (SCM) in
the system clock control register (SYCC).
Check:
Before switching the CPU to subclock mode immediately after turning the power on, wait for
at least the subclock oscillation stabilization delay time generated by the watch prescaler by
means of software.
Operation in Subclock Mode
During normal operation in subclock mode (sub-RUN mode), only the subclock operates with
the main clock stopping oscillation. Using the lower-speed clock as the operating clock reduces
power consumption.
In subclock mode, all the functions other than the timebase timer work the same as in main
clock mode. When standby mode is specified during operation in subclock mode, the CPU can
enter sub-sleep, sub-stop, or watch mode.
Returning from subclock mode to main clock mode
Writing "1" to the system clock select bit (SCS) in the system clock control register (SYCC)
wakes up the CPU from subclock mode to main clock mode.
Note, however, that the CPU restarts operation in main clock mode after the main clock
oscillation stabilization delay time has passed. The oscillation stabilization delay time can be
selected from among four types depending on the settings of the oscillation stabilization delay
time select bits (WT1 and WT0) in the system clock control register (SYCC).
Check:
Do not overwrite the oscillation stabilization delay time select bits (SYCC: WT1 and WT0)
upon switching from the subclock to main clock (SYCC: SCS = "1"). Also, do not rewrite the
bits during the main clock oscillation stabilization delay time. Before rewriting them, use the
system clock monitor bit to check that the operating clock has been switched to the main
clock (SYCC: SCM = "1").
When the CPU is reset from subclock mode to main clock mode, the product with the power-on
reset function takes the main clock oscillation stabilization delay time. In contrast, the product
without the power-on reset function does not take the oscillation stabilization delay time unless
the reset is a software or watchdog reset.
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