Standby Control Register (Stbc); Figure 3.7-1 Standby Control Register (Stbc) - Fujitsu F2MC-8L Series Hardware Manual

3.7.5

Standby Control Register (STBC)

The standby control register (STBC) controls the changing to sleep mode, stop mode,
or watch mode, sets the pin states in stop or watch mode, and initiates software
resets.
Standby Control Register (STBC)
Address
0008
H
R/W : Readable and writable
W : Write-only
— : Unused
X : Indeterminate
: Initial value

Figure 3.7-1 Standby Control Register (STBC)

Bit 7 Bit 6 Bit 5 Bit 4
STP SLP SPL RST
W W R/W W
TMD
0
1
RST
0
1
SPL
0
1
SLP
0
1
STP
0
1
3.7 Standby Modes (Low-power Consumption)
Bit 3 Bit 2 Bit 1
TMD — —
W
Watch bit
Enabled only in subclock mode (SYCC: SCS = "0")
Read
Reading always returns "0".
—
Software reset bit
Read
—
Reading always returns "1".
Pin state specification bit
External pins hold their states prior to entering stop mode.
External pins go to high-impedance state on entering stop mode.
Sleep bit
Read
Reading always returns "0".
—
Stop bit
Read
Reading always returns "0".
—
Bit 0 Initial value
— 00010XXX
B
Write
No effect on operation
Change to watch mode.
Write
Generates a reset signal for
four instruction cycles.
No effect on operation
Write
No effect on operation
Change to sleep mode.
Write
No effect on operation
Change to stop mode.
81