Figure B.1-3 Bit Direct Addressing; Figure B.1-4 Index Addressing; Figure B.1-5 Pointer Addressing - Fujitsu F2MC-8L Series Hardware Manual

APPENDIX B Overview of Instructions
Bit direct addressing
Indicated by "dir: b" in the instruction list. Used to access the area between "0000
"00FF
H
operand specifies the lower one byte of the address, and the lower three bits of the operation
code specify the bit position. Figure B.1-3 shows an example.
Index addressing
Indicated by "@IX+off" in the instruction list. Used to access the entire 64-Kbyte area. Index
addressing generates the address by adding the sign-extended contents of the first operand to
the index register (IX). Figure B.1-4 shows an example.
Pointer addressing
Indicated by "@EP" in the instruction list. Used to access the entire 64-Kbyte area. Pointer
addressing uses the extra pointer (EP) as the address. Figure B.1-5 shows an example.
General-purpose register addressing
Indicated by "Ri" in the instruction list. Used to access register banks in the general-purpose
register area. For general-purpose register addressing, the upper one byte of the address is
fixed at "01" and the lower one byte is generated from the register bank pointer (RP) and the
lower three bits of the operation code. The CPU accesses the resulting address. Figure B.1-6
310
" in bit units. For bit direct addressing, the upper one byte of the address is "00

Figure B.1-3 Bit Direct Addressing

SETB
MOVW A,@IX+5 AH
27A5
IX
MOVW
27A5
EP
34H : 2
0034

Figure B.1-4 Index Addressing

27FF 12
H H
+
H
2800 34
H H

Figure B.1-5 Pointer Addressing

A,@EP
27A5 12
H
H
27A6 34
H
7 6 5 4 3 2 1 0
XXXXX1 XX
H
B
A 1234
H
H
A 1234
H
H
" and
H
", the
H