Table B.4-2 Arithmetic Operation Instructions - Fujitsu F2MC-8L Series Hardware Manual

Table B.4-1 Transfer Instructions (Continued)
No. Mnemonic
27 MOVW A,@EP
28 MOVW A,EP
29 MOVW EP,#d16
30 MOVW IX,A
31 MOVW A,IX
32 MOVW SP,A
33 MOVW A,SP
34 MOV @A,T
35 MOVW @A,T
36 MOVW IX,#d16
37 MOVW A,PS
38 MOVW PS,A
39 MOVW SP,#d16
40 SWAP
41 SETB dir: b
42 CLRB dir: b
43 XCH A,T
44 XCHW A,T
45 XCHW A,EP
46 XCHW A,IX
47 XCHW A,SP
48 MOVW A,PC
Check:
• The automatic transfer to the T register is TL <-- AL for instructions that perform a byte
transfer to A.
• Operands in more than one operand instruction must be stored in the order in which their
mnemonics are written.
Arithmetic Operation Instructions

Table B.4-2 Arithmetic Operation Instructions

No. Mnemonic
1 ADDC A,Ri
2 ADDC A,#d8
3 ADDC A,dir
4 ADDC A,@IX+off
~ # Operation
4 1 (AH) <-- ((EP)), (AL) <-- ((EP) + 1 )
2 1 (A) <-- (EP)
3 3 (EP) <-- d16
2 1 (IX) <-- (A)
2 1 (A) <-- (IX)
2 1 (SP) <-- (A)
2 1 (A) <-- (SP)
3 1 ((A)) <-- (T)
4 1 ((A)) <-- (TH), ((A) + 1 ) <-- (TL)
3 3 (IX) <-- d16
2 1 (A) <-- (PS)
2 1 (PS) <-- (A)
3 3 (SP) <-- d16
2 1 (AH) <--> (AL)
4 2 (dir): b <-- 1
4 2 (dir): b <-- 0
2 1 (AL) <--> (TL)
3 1 (A) <--> (T)
3 1 (A) <--> (EP)
3 1 (A) <--> (IX)
3 1 (A) <--> (SP)
2 1 (A) <-- (PC)
~ # Operation
3 1 (A) <-- (A) + (Ri) + C
2 2 (A) <-- (A) + d8 + C
3 2 (A) <-- (A) + (dir) + C
4 2 (A) <-- (A) +((IX) + off ) + C
APPENDIX B Overview of Instructions
TL TH AH N Z V C
AL AH dH + + - -
- - dH
- - -
- - -
- - dH
- - -
- - dH
- - -
- - -
- - -
- - dH
- - - + + + +
- - -
- - AL
- - -
- - -
AL - -
AL AH dH
- - dH
- - dH
- - dH
- - dH
TL TH AH N Z V C
- - - + + + +
- - - + + + +
- - - + + + +
- - - + + + +
OP code
C7
- - - - F3
- - - - E7
- - - - E2
- - - - F2
- - - - E1
- - - - F1
- - - - 82
- - - - 83
- - - - E6
- - - - 70
71
- - - - E5
- - - - 10
- - - - A8 to AF
- - - - A0 to A7
- - - - 42
- - - - 43
- - - - F7
- - - - F6
- - - - F5
- - - - F0
OP code
28 to 2F
24
25
26
319