3.7.10 Notes On Using Standby Modes - Fujitsu F2MC-8L Series Hardware Manual

3.7.10 Notes on Using Standby Modes

The CPU does not change to a standby mode if an interrupt request occurs from a
peripheral function when a standby mode is set in the standby control register (STBC).
Also, if an interrupt is used to wake up from a standby mode to the normal operating
state, the operation after wake-up differs depending on whether or not the interrupt
request is accepted.
Changing to a Standby Mode and Interrupts
If an interrupt request with an interrupt priority level higher than "11" occurs from a peripheral
function to the CPU, writing "1" to the stop bit (STP), sleep bit (SLP), or watch bit (TMD) in the
standby control register (STBC) is ignored. Therefore, the CPU does not change to a standby
mode. (The CPU also does not change to the standby mode after completing interrupt
processing.)
This does not depend on whether or not the CPU accepts the interrupt.
Even if the CPU is currently performing interrupt processing, the interrupt request flag bit is
cleared and, if no other interrupt request is present, the device can change to a standby mode.
Wake-up from Standby Mode by Interrupt
If an interrupt request with an interrupt level higher than "11" occurs from a peripheral function
or others during sleep or stop mode, the CPU wakes up from a standby mode. This does not
depend on whether or not the CPU accepts the interrupt.
After wake-up from a standby mode, the CPU performs the normal interrupt operations. If the
priority level set in the interrupt level setting register (ILR1 to ILR3) corresponding to the
interrupt request is higher than the interrupt level bits in the condition code register (CCR: IL1,
IL0), and if the interrupt enable flag is enabled (CCR: I = "1"), the CPU branches to the interrupt
processing routine. If the interrupt is not accepted, operation restarts from the subsequent
instruction following the instruction that activated a standby mode.
To prevent control from branching to an interrupt processing routine after wake-up, take
measures such as disabling interrupts before setting a standby mode.
Notes on Setting Standby Mode
When setting the standby control register (STBC) to specify a standby mode, follow the bit
settings listed in Table 3.7-10. If "1" is written to all of the three bits in the STBC register at the
same time, priority is given to stop mode, watch mode, and sleep mode in this order. Only one
of the bits should be set to "1".
Do not cause the CPU to enter stop, sleep, or watch mode immediately after switching to main
clock mode from subclock mode (SYCC: SCS = "0" --> "1"). Before entering any of the standby
modes, ensure that the clock monitor bit (SCM) in the system control register (SYCC) has been
set to "1".
3.7 Standby Modes (Low-power Consumption)
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