Operation Of Timebase Timer; Figure 5.5-1 Interval Timer Function Settings - Fujitsu F2MC-8L Series Hardware Manual

5.5

Operation of Timebase Timer

The timebase timer has the interval timer function and the clock supply function for
some peripherals.
Operation of Interval Timer Function (Timebase Timer)
Figure 5.5-1 shows the settings required to operate the interval timer function.
Provided the main clock is oscillating, the timebase timer counter continues to count up in
synchronization with the internal count clock (divide-by-two main clock source oscillation).
After being cleared (TBR = "0"), the counter restarts counting-up from zero. The timebase timer
sets the overflow interrupt request flag bit (TBOF) to "1" when an overflow occurs on the interval
timer bit. Consequently, the timebase timer generates interrupt requests at fixed intervals (the
selected interval time), based on the time that the counter is cleared.
Operation of Clock Supply Function
The timebase timer is also used as a timer to generate the oscillation stabilization delay time for
the main clock. The time from when the counter starts counting-up from zero until an overflow
occurs on the oscillation stabilization delay time bit is the oscillation stabilization delay time. The
oscillation stabilization delay time is selected from among four types depending on the
oscillation stabilization delay time select bits (WT1 and WT0) in the system clock control register
(SYCC).
The timebase timer also provides the clock for the watchdog timer, and buzzer output. Clearing
the timebase timer counter affects the operation of the continuous activation cycle of the buzzer
output. This also simultaneously clears the watchdog timer counter if the timebase timer output
is selected (WDTC: CS="0").
Timebase Timer Operation
The operations of the following states are shown in figure 5.5-2.
• A power-on reset occurs.
• The CPU changes to sleep mode during operation of the interval timer function in main clock
mode.
• The CPU changes to main-stop mode.
• A counter clear request occurs.
The timebase timer is cleared by changing to subclock mode or main-stop mode, and stops
operation. The timebase timer counts the oscillation stabilization delay time after wake-up from
subclock mode or main-stop mode.

Figure 5.5-1 Interval Timer Function Settings

Bit 7 Bit 6 Bit 5
TBTC TBOF TBIE —
0 1
Bit 4 Bit 3 Bit 2 Bit 1
— — TBC1 TBC0
5.5 Operation of Timebase Timer
Bit 0
TBR
: Used bit
1 : Set "1".
0
0 : Set "0".
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