Fujitsu F2MC-8L Series Hardware Manual page 20

Figure 3.7-4 State Transition Diagram 3 (Product with Power-on Reset Function) ....................................... 89
Figure 3.7-5 State Transition Diagram 3 (Product without Power-on Reset Function) .................................. 89
Figure 3.8-1 Mode Data Structure ................................................................................................................. 95
Figure 3.8-2 Memory Access Selection Operation ........................................................................................ 96
Figure 4.2-1 Block Diagram of Port 0 Pin ................................................................................................... 102
Figure 4.3-1 Block Diagram of Port 1 Pin .................................................................................................... 108
Figure 4.4-1 Block Diagram of Port 2 Pin .................................................................................................... 114
Figure 4.5-1 Block Diagram of Port 3 Pins (P30 to P32, P34 to P36) .......................................................... 118
Figure 4.5-2 Block Diagram of Port 3 Pins (P33, P37) ................................................................................ 118
Figure 4.6-1 Block Diagram of Port 4 Pin .................................................................................................... 125
Figure 4.7-1 Connection Example for an Eight-Segment LED .................................................................... 128
Figure 5.2-1 Block Diagram of Timebase Timer .......................................................................................... 134
Figure 5.3-1 Timebase Timer Control Register (TBTC) ............................................................................... 136
Figure 5.5-1 Interval Timer Function Settings .............................................................................................. 139
Figure 5.5-2 Timebase Timer Operation ...................................................................................................... 140
Figure 5.6-1 Effect on Buzzer Output of Clearing Timebase Timer ............................................................. 142
Figure 6.2-1 Block Diagram of Watchdog Timer .......................................................................................... 147
Figure 6.3-1 Watchdog Timer Control Register (WDTC) ............................................................................. 149
Figure 6.4-1 Watchdog Timer Clear and Interval Time ................................................................................ 152
Figure 7.2-1 Block Diagram of 8/16-bit Timer/Counter ................................................................................ 161
Figure 7.3-1 Block Diagram of 8/16-bit Timer/Counter Pin (P33/EC/SCO) ................................................. 164
Figure 7.3-2 Block Diagram of 8/16-bit Timer/Counter Pin (P34/TO/INT0) ................................................. 164
Figure 7.4-1 8/16-bit Timer/Counter Registers ............................................................................................ 165
Figure 7.4-2 Timer 1 Control Register (T1CR) ............................................................................................. 166
Figure 7.4-3 Timer 2 Control Register (T2CR) ............................................................................................. 169
Figure 7.4-4 Timer 1 Data Register (T1DR) ................................................................................................. 171
Figure 7.4-5 Timer 2 Data Register (T2DR) ................................................................................................. 173
Figure 7.6-1 Settings for Interval Timer Function (Timer 1) ......................................................................... 177
Figure 7.6-2 Settings for Interval Timer Function (Timer 2) ......................................................................... 177
Figure 7.6-3 Operation of Interval Timer Function (Timer 1) in 8-bit Mode .................................................. 178
Figure 7.6-4 Settings for Interval Timer Function (in 16-bit Mode) .............................................................. 178
Figure 7.7-1 Settings for Counter Function (in 8-bit Mode) .......................................................................... 179
Figure 7.7-2 Settings for Counter Function (in 16-bit Mode) ........................................................................ 180
Figure 7.7-3 Operation of Counter Functions in 16-bit Mode ....................................................................... 181
Figure 7.8-1 Initialization Equivalent Circuit for Square Wave Output ......................................................... 182
Figure 7.8-2 Initial setup operation of the square wave output .................................................................... 183
Figure 7.10-1 Counter Operation during Subclock or Standby Modes and Operation Halt ........................... 186
Figure 7.11-1 Operation When Timer Stop Bit is Used .................................................................................. 187
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