Figure 4.2-1 Block Diagram Of Port 0 Pin; Table 4.2-2 Correspondence Between Pins And Registers For Port 0 - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 4 I/O PORTS
Block Diagram of Port 0
SPL: Pin state specification bit in the standby control register (STBC)
Check:
External interrupt circuits always input pin values. To use a pin as a normal I/O port,
therefore, the external interrupt circuit corresponding to the pin must be disabled.
details, see Chapter 11 "External Interrupt Circuit 2".
Port 0 Registers
The port 0 registers consist of PDR0 and DDR0.
Each bit in these registers has a one-to-one relationship with a port 0 pin respectively.
Table 4.2-2 shows the correspondence between pins and registers for port 0.

Table 4.2-2 Correspondence between Pins and Registers for Port 0

Port
PDR0, DDR0
Port 0
Corresponding pin
102

Figure 4.2-1 Block Diagram of Port 0 Pin

PDR (Port data register)
PDR read
PDR read (for bit manipulation instructions)
Output latch
PDR write
DDR
DDR write (Port data direction register)
Stop or watch mode (SPL=1)
Correspondence between register bit and pin
Bit 7
P07
To externel interrupt
(MB89120A only)
Stop or watch mode
(SPL=1)
Bit 6 Bit 5 Bit 4
P06 P05 P04
Pull-up resistor
(optional)
Approx. 50 k /5.0 V
P-ch
P-ch
N-ch
Bit 3 Bit 2 Bit 1
P03 P02 P01
Pin
For
Bit 0
P00