Operation Of Port 4; Table 4.6-4 Port 4 Pin State - Fujitsu F2MC-8L Series Hardware Manual

4.6.2

Operation of Port 4

This section describes the operations of the port 4.
Operation of Port 4
Operation as an output port
• Writing data to the PDR4 register stores the data in the output latch. When the output latch
value is "0", the output transistor turns "ON" and an "L" level is output from the pin. When the
output latch value is "1", the transistor turns "OFF" and the pin goes to the high-impedance
state. If a pull-up is provided to the output pin, the pin goes to the pull-up state when the
output latch value is "1".
• Reading the PDR4 register always returns the output latch value.
Operation at reset
Resetting the CPU initializes the PDR4 register values to "1". This turns all the output transistors
"OFF" and sets the pins to the high-impedance state.
Operation in stop mode or watch mode
The output transistors are forcibly turned "OFF" and the pins go to the high-impedance state if
the pin state specification bit in the standby control register (STBC: SPL) is "1" when the device
changes to stop or watch mode.
Table 4.6-4 lists the port 4 pin states.

Table 4.6-4 Port 4 Pin State

Pin name
P40/AN0 to P43/AN3
SPL: Pin state specification bit in the standby control register (STBC)
Hi-z: High impedance
Tip:
Pins with a pull-up resistor (optional) go to the "H" level (pull-up state) rather than to the high-
impedance state when the output transistor is turned "OFF".
Normal operation
Main-sleep mode
Main-stop mode (SPL = 0)
Sub-sleep mode
Sub-stop mode (SPL = 0)
Watch mode (SPL = 0)
Output-only ports/analog input
Main-stop mode (SPL = 1)
Sub-stop mode (SPL = 1)
Watch mode (SPL = 1)
Hi-z
4.6 Port 4
Reset
Hi-z
127