Fujitsu F2MC-8L Series Hardware Manual page 21

Figure 7.11-2 Error on Starting Counter Operation ....................................................................................... 188
Figure 8.2-1 Block Diagram of 8-bit Serial I/O ............................................................................................ 195
Figure 8.3-1 Block Diagram of 8-bit Serial I/O Pins .................................................................................... 198
Figure 8.4-1 8-bit Serial I/O-1 Registers ..................................................................................................... 199
Figure 8.4-2 Serial Mode Register (SMR) ................................................................................................... 200
Figure 8.4-3 Serial Data Register (SDR) ..................................................................................................... 203
Figure 8.6-1 Serial Output Settings (When Using Internal Shift Clock) ....................................................... 205
Figure 8.6-2 Serial Output Settings (When Using External Shift Clock) ..................................................... 205
Figure 8.6-3 8-bit Serial Output Operation .................................................................................................. 206
Figure 8.7-1 Serial Input Settings (When Using Internal Shift Clock) ......................................................... 207
Figure 8.7-2 Serial Input Settings (When Using External Shift Clock) ........................................................ 207
Figure 8.7-3 8-bit Serial Input Operation ..................................................................................................... 208
Figure 8.8-1 Operation in Sleep Mode (Internal Shift Clock) ...................................................................... 209
Figure 8.8-2 Operation in Stop or Watch Mode (Internal Shift Clock) ......................................................... 209
Figure 8.8-3 Operation during Halt (Internal Shift Clock) ............................................................................ 210
Figure 8.8-4 Operation in Sleep Mode (External Shift Clock) ..................................................................... 210
Figure 8.8-5 Operation in Stop or Watch Mode (External Shift Clock) ........................................................ 211
Figure 8.8-6 Operation during Halt (External Shift Clock) ........................................................................... 211
Figure 8.9-1 Idle State of Shift Clock .......................................................................................................... 212
Figure 8.10-1 Connection Example for 8-bit Serial I/O (Interface between Two MB89120/120As) .............. 213
Figure 8.10-2 Bidirectional Serial I/O Operation ........................................................................................... 214
Figure 9.2-1 Block Diagram of Buzzer Output ............................................................................................ 222
Figure 9.3-1 Block Diagram of P37/BZ/(RCO) Pin ...................................................................................... 223
Figure 9.4-1 Buzzer Output Register .......................................................................................................... 224
Figure 9.4-2 Buzzer Register (BZCR) ......................................................................................................... 225
Figure 10.2-1 Block Diagram of External Interrupt Circuit 1 .......................................................................... 231
Figure 10.3-1 Block Diagram of External Interrupt Circuit 1 Pins .................................................................. 234
Figure 10.4-1 External Interrupt Circuit Registers ......................................................................................... 235
Figure 10.4-2 External Interrupt 1 Control Register 1 (EIC1) ........................................................................ 236
Figure 10.4-3 External Interrupt 1 Control Register 2 (EIC2) ........................................................................ 238
Figure 10.6-1 External Interrupt Circuit 1 Settings ........................................................................................ 241
Figure 10.6-2 External Interrupt (INT0) Operation ........................................................................................ 242
Figure 11.2-1 Block Diagram of External Interrupt Circuit 2 .......................................................................... 247
Figure 11.3-1 Block Diagram of External Interrupt Circuit 2 Pins .................................................................. 250
Figure 11.4-1 External Interrupt Circuit 2 Registers ...................................................................................... 251
Figure 11.4-2 External Interrupt Circuit 2 Control Register(EIE2) ................................................................. 252
Figure 11.4-3 External Interrupt 2 Flag Register (EIF2) ................................................................................ 254
Figure 11.6-1 External Interrupt Circuit 2 Settings ........................................................................................ 256
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