Operation Of Port 2; Table 4.4-4 Port 2 Pin State - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 4 I/O PORTS
4.4.2

Operation of Port 2

This section describes the operations of port 2.
Operation of Port 2
Operation as an output-only port
• Writing data to the PDR2 register stores the data in the output latch and outputs the data to
the pin via the output buffer.
Operation at reset
Resetting the CPU initializes the PDR2 register values (bits) to all "0"s so that the pins output
the "L" level.
Operation in stop or watch mode
The output buffer is forcibly set to "OFF" and the pins go to the high-impedance state if the pin
state specification bit in the standby control register (STBC: SPL) is "1" when the device
changes to stop or watch mode.
Table 4.4-4 lists the port 2 pin states.

Table 4.4-4 Port 2 Pin State

Pin name
P20 to P27
SPL: Pin state specification bit in the standby control register (STBC)
Hi-z: High impedance
116
Normal operation
Main-sleep mode
Main-stop mode (SPL = 0)
Sub-sleep mode
Sub-stop mode (SPL = 0)
Watch mode (SPL = 0)
Output-only ports
Main-stop mode (SPL = 1)
Sub-stop mode (SPL = 1)
Watch mode (SPL = 1)
Hi-z
Reset
Hi-z