Fujitsu F2MC-8L Series Hardware Manual page 22

Figure 11.6-2 Operation of External Interrupt Circuit 2 (INT20) ..................................................................... 257
Figure 12.2-1 Block Diagram of Watch Prescaler .......................................................................................... 264
Figure 12.3-1 Watch Prescaler Control Register (WPCR) ............................................................................. 266
Figure 12.5-1 Interval Timer Function Settings .............................................................................................. 269
Figure 12.5-2 Watch Prescaler Operation ..................................................................................................... 270
Figure 12.6-1 Effect of Clearing Watch Prescaler on Buzzer Output ............................................................. 272
Figure 13.2-1 Block Diagram of Remote-control Transmission Frequency Generator .................................. 281
Figure 13.3-1 Block Diagram of Remote-control Transmission Frequency Generator Pin(P37/BZ/RCO) .... 283
Figure 13.4-1 Remote-control Transmission Frequency Generator Registers .............................................. 284
Figure 13.4-2 Remote-control Transmission Frequency Control Register 1 (RCR1) .................................... 285
Figure 13.4-3 Remote-control Transmission Frequency Control Register 2 (RCR2) .................................... 287
Figure 13.5-1 Settings for Remote-control Transmission Frequency Generator ........................................... 289
Figure 13.5-2 Operation of Remote-control Transmission Frequency Generator .......................................... 290
Figure 13.6-1 Changing Set Values during Operation of Remote-control Transmission
Frequency Generator .............................................................................................................. 292
Figure 13.6-2 Remote-control Output Function ............................................................................................. 292
Figure 13.6-3 Error on Starting Counter Operation ........................................................................................ 293
Figure 14.2-1 Block Diagram of Peripheral Control Clock Output ................................................................. 297
Figure 14.3-1 Block Diagram of Peripheral Control Clock Output Pin ........................................................... 298
Figure 14.3-2 Peripheral Control Clock Register (SCGC) ............................................................................. 299
Figure B-1 Instruction Code and Instruction Map ...................................................................................... 307
Figure B.1-1 Direct Addressing .................................................................................................................... 309
Figure B.1-2 Extended Addressing .............................................................................................................. 309
Figure B.1-3 Bit Direct Addressing ............................................................................................................... 310
Figure B.1-4 Index Addressing ..................................................................................................................... 310
Figure B.1-5 Pointer Addressing .................................................................................................................. 310
Figure B.1-6 General-Purpose Register Addressing .................................................................................... 311
Figure B.1-7 Immediate Addressing ............................................................................................................. 311
Figure B.1-8 Vector Addressing ................................................................................................................... 312
Figure B.1-9 Relative Addressing ................................................................................................................. 312
Figure B.1-10 Inherent Addressing ................................................................................................................ 312
Figure B.2-1 JMP @A .................................................................................................................................. 313
Figure B.2-2 MOVW A, PC ........................................................................................................................... 313
Figure B.2-3 MULU A ................................................................................................................................... 314
Figure B.2-4 DIVU A .................................................................................................................................... 314
Figure B.2-5 XCHW A,PC ............................................................................................................................ 315
Figure B.2-6 Example Using XCHW A,PC ................................................................................................... 315
Figure B.2-7 Execution Example of CALLV #3 ............................................................................................ 316
xvii