8-Bit Serial I/O Interrupts; Table 8.5-1 Register And Vector Table For 8-Bit Serial I/O Interrupts - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 8 8-BIT SERIAL I/O
8.5

8-bit Serial I/O Interrupts

The 8-bit serial I/O can generate interrupt requests after completion of the serial input
and output of the 8-bit data.
Interrupt during Serial I/O Operation
The 8-bit serial I/O performs the serial input operation and serial output operation at the same
time. When the serial transfer starts, the data in the serial data register (SDR) is input and
output one bit at a time, synchronized with the cycle of the selected shift clock. Then, the
interrupt request flag bit (SMR: SIOF) is set to "1" on the rising edge of the shift clock of the
eighth bit.
At this time, an interrupt request (IRQ4) to the CPU is generated if the interrupt request enable
bit is enabled (SMR: SIOE = "1").
Write "0" to the SIOF bit in the interrupt processing routine to clear the interrupt request. The
SIOF bit is set after completing 8-bit serial output, regardless of the SIOE bit value.
Tip:
The interrupt request flag bit is not set (SMR: SIOF = "1") if serial transfer is stopped (SMR:
SST = "0") at the same time as serial data transfer completes for the serial I/O operation. An
interrupt request is generated immediately if the SIOF bit is "1" when the SIOE bit is changed
from disabled to enabled ("0" --> "1").
Register and Vector Table for 8-bit Serial I/O Interrupts

Table 8.5-1 Register and Vector Table for 8-bit Serial I/O Interrupts

Interrupt
IRQ4
Reference:
See Section 3.4.2, "Interrupt Processing" for details on the interrupts operation.
204
Interrupt level setting register
Register
ILR2 (007D ) L41 (Bit 1)
H
Setting bits
L40 (Bit 0)
Vector table address
Upper Lower
FFF2 FFF3
H H