Figure 8.8-3 Operation During Halt (Internal Shift Clock); Figure 8.8-4 Operation In Sleep Mode (External Shift Clock) - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 8 8-BIT SERIAL I/O
Operation during halt
Halting operation during transfer (SMR: SST = "0") halts the transfer and clears the shift clock
counter, as shown in Figure 8.8-3. Therefore, the device being communicated with must also be
initialized. In serial output operation, set data to the SDR register again before reactivating.
SCK output
SST bit
SIOF bit
SO pin output
Using External Shift Clock
Operation in sleep mode
In sleep mode, serial I/O operation does not halt but transfer continues, as shown in Figure 8.8-
4.
SCK input
SST bit
SIOF bit
SO pin output
SLP bit
(STBC register)
210

Figure 8.8-3 Operation during Halt (Internal Shift Clock)

#0 #1 #2

Figure 8.8-4 Operation in Sleep Mode (External Shift Clock)

#0 #1 #2
Operation halts.
Reset SDR register
#3 #4 #5
#3 #4 #5 #6 #7
Sleep mode
Wake-up from sleep mode by IRQ4
Operation reactivated.
#0 #1
Clock for next data
Transfer disabled state
Cleared by the program.