Fujitsu F2MC-8L Series Hardware Manual page 266

Table 10.4-2 External Interrupt 1 Control Register 2 (EIC2) Bits (Continued)
Bit
SL21, SL20:
Bit 2 Edge polarity
Bit 1 selection bit
2
EIE2:
Interrupt
Bit 0
request
enable bit 2
• This bit selects the edge polarity that triggers interrupts when
detected on pulses input to external interrupt pin INT2.
• These bits defect the edge polarity at the rising edge when the
bit value is "00 ", at the falling edge when the value is "01
B
and at both edges when the value is "10
This bit enables or disables an interrupt request output to the
CPU. An interrupt request is output when both this bit and the
external interrupt request flag bit 2 (EIR2) are "1".
10.4 External Interrupt Circuit 1 Registers
Function
B
",
B
or 11 ".
B
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