14.3 Peripheral Control Clock Output Pin; Figure 14.3-1 Block Diagram Of Peripheral Control Clock Output Pin - Fujitsu F2MC-8L Series Hardware Manual

CHAPTER 14 PERIPHERAL CONTROL CLOCK OUTPUT

14.3 Peripheral Control Clock Output Pin

This section describes the peripheral control clock output pin and provides its block
diagram.
Peripheral Control Clock Output Pin
The peripheral control clock output uses the P33/EC/SCO pin.
P33/EC/SCO pin
The P33/EC/SCO pin serves as a general-purpose I/O port pin (P33), 8/16-bit timer/counter
external clock input pin (EC), or as peripheral control clock output pin (SCO).
SCO:
Block Diagram of Peripheral Control Clock Output Pin

Figure 14.3-1 Block Diagram of Peripheral Control Clock Output Pin

PDR (Port data register)
PDR read
PDR read
(for bit manipulation instructions)
PDR write
DDR write
SPL: Pin state specification bit in the standby control register (STBC)
Tip:
If a pull-up resistor option has been selected for the pin, the level at the pin becomes "H" at a
reset or in stop or watch mode (SPL = "1").
298
This pin outputs the selected peripheral control clock signal. When peripheral
control clock output is enabled (SCGC: SCG1, SCG0 = other than "00
P33/EC/SCO pin automatically serves as the SCO pin for peripheral control clock
output, regardless of the value (bit 3) in the port data direction register (DDR3).
From peripheral
control clock output
Output latch
DDR
(Port data direction register)
Stop or watch mode (SPL= "1")
To 8/16-bit
timer/counter input
From clock
output enable
Stop or watch
mode (SPL= "1")
Input buffer
"), the
B
Pull-up resistor
(optional)
Approx. 50 k /5.0 V
P-ch
P-ch
Pin
N-ch