Table 3.7-4 Switching to and from Standby Mode (Product with Power-on Reset Function in Dual-clock
Configuration)
State transition
Wake-up from stop mode
Transition to watch mode
Wake-up from watch mode
STBC:
*:
Reference:
In standby mode, neither software nor watchdog resets do not occur because the CPU and
watchdog timer are stopped.
main clock mode
(5)
External interrupt
(6)
End of main clock oscillation
stabilization delay time
(Timebase timer output)
(7)
External reset
(8)
External reset (in oscillation
stabilization delay time)
Standby control register
Transition to watch mode is enabled only from sub-RUN state (SYCC: SCS = "0").
3.7 Standby Modes (Low-power Consumption)
Transition conditions
<5>
<6>
<7>
<8>
-
<9>
<10>
-
<11>
Subclock mode
External interrupt
End of subclock oscillation
stabilization delay time
(Watch prescaler output)
External reset
External reset (in oscillation
stabilization delay time)
STBC : TMD="1"*
External interrupt or watch
interrupt
External reset
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