Table 8.4-1 Serial Mode Register (Smr) Bits - Fujitsu F2MC-8L Series Hardware Manual

Table 8.4-1 Serial Mode Register (SMR) Bits

Bit
SIOF:
Bit 7
Interrupt request flag bit
SIOE:
Bit 6 Interrupt request enable
bit
SCKE:
Bit 5 Shift clock output enable
bit
SOE:
Bit 4 Serial data output enable
bit
Bit 3 CKS1, CKS0:
Bit 2 Shift clock selection bits
BDS:
Bit 1 Transfer direction
selection bit
• This bit is set to "1" when the serial output operation has output 8
bits of serial data or the serial input operation has input 8 bits of
serial data. An interrupt request is output when both this bit and the
interrupt request enable bit (SIOE) are "1".
• Writing "0" clears this bit. Writing "1" has no effect and does not
change the bit value.
This bit enables or disables an interrupt request output to the CPU.
An interrupt request is output when both this bit and the interrupt
request flag bit (SIOF) are "1".
• This bit controls the shift clock input and output.
• The P30/SCK pin functions as the shift clock input pin when this bit
is set to "0" and as the shift clock output pin when set to "1".
Notes:
• Set the P30/SCK pin as an input port when using this pin as the
shift clock input. Also, selects external shift clock operation (CKS1,
CKS0 = "11B") in the shift clock selection bits.
• Select internal shift clock operation (CKS1, CKS0 = other than
"11B") when using this pin as a shift clock output (SCKE = "1").
Tips:
• The pin functions as the SCK output pin when shift clock output
is enabled (SCKE = "1"), regardless of the state of the general-
purpose port (P30).
• Set to shift clock input operation (SCKE = "0") when using this
pin as a general-purpose port (P30).
The P31/SO pin functions as a general-purpose port (P31) when this
bit is set to "0" and as the serial data output pin (SO) when set to "1".
Tip:
The pin functions as the SO pin when serial data output is enabled
(SOE= "1"), regardless of the state of the general-purpose port
(P31).
• These bits select the shift clock from one external and three
internal shift clocks.
• Setting these bits to other than "11
In this case, the shift clock is output from the SCK pin if the shift
clock output enable bit (SCKE) is "1".
• Setting these bits to "11
inputs the shift clock from the SCK pin if shift clock input is
enabled.
This bit selects whether serial data is transferred with the least
significant bit first (LSB first, BDS = "0") or the most significant bit first
(MSB first, BDS = "1").
Note:
If this bit is updated after data is written to the serial data register
(SDR) for replacing the upper and lower sides of data with each
other to read or write to the SDR register, the written data is made
invalid.
8.4 8-bit Serial I/O Registers
Function
" selects an internal shift clock.
B
" selects the external shift clock. This
B
201