Fujitsu F2MC-8L Series Hardware Manual page 91

CHAPTER 3 CPU
Subclock oscillator
This oscillator is the oscillation circuit for the subclock. It always oscillates except in sub-stop
mode. The oscillator does not operate with the single-clock option selected.
System clock selector
This selector selects one of the four different clock signals obtained by dividing the oscillation
frequency of the main clock or the subclock signal and supplies it to the clock controller.
Clock controller
Supply of the operating clock to the CPU and peripheral circuits is properly controlled for the
normal operation (RUN) and each standby mode (sleep, stop or watch).
Also, supply of the clock to the CPU is stopped until the clock supply stop signal in the
oscillation stabilization delay time selector is released.
Oscillation stabilization delay time selector
This register selector selects any of four types of the main clock oscillation stabilization delay
time generated from the timebase timer and the subclock oscillation stabilization delay time
generated from the watch prescaler for the clock mode, standby mode and reset to be output as
the clock supply stop signal to the CPU.
System clock control register (SYCC)
This register selects the clock mode, main clock speed, and main clock oscillation stabilization
delay time. It also checks the clock status.
Standby control register (STBC)
This register controls changing from normal operation (RUN) to the standby modes, sets the pin
states in the stop or watch mode, and initiates software reset.
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