Table 5-1 Function Of Each Bit Of Low-Power Consumption Mode Control Register (Lpmcr) - Fujitsu MB90420/5 (A) Series Hardware Manual

MB90420/5 (A) SERIES F

Table 5-1 Function of Each Bit of Low-power Consumption Mode Control Register (LPMCR)

Bit Name
bit 7 STP: Stop mode
bit
bit 6 SLP: Sleep mode
bit
bit 5 SPL: Pin state
specification bit
(In timer, time-
base timer or
stop mode)
bit 4 RST: Internal
reset signal
generate bit
bit 3 TMD: Timer,
time-base timer
mode bit
bit 2 CG1, CG0: CPU
bit 1 suspended clock
cycle count select
bit
bit 0 RESV: Reserved
bit
2
MC-16LX FAMILY 16-BIT MICROCONTROLLERS HARDWARE MANUAL
• This bit specifies a transition to the time-base timer mode or the stop mode.
• When 1 is written to this bit and when the PLL clock is selected (CKSCR: MCS = 0), a
transition to the time-base timer mode is performed. When 1 is written to this bit and
when the oscillation clock is selected (CKSCR: MCS = 1), a transition to the stop
mode is performed. The state of the MCS bit determines the time-base timer mode or
stop mode even when 1 is written to the STP bit during a transition of the clock
selection.
• When 0 is written to this bit, operation is not affected.
• This bit is cleared to 0 at a reset, a time-base timer cancellation or a stop cancellation.
• 0 is always read from this bit.
• This bit specifies a transition to the sleep mode.
• When 1 is written to this bit, a transition is performed to the sleep mode.
• When 0 is written to this bit, operation is not affected.
• This bit is cleared to 0 at a reset, a sleep cancellation or a stop cancellation. When 1
is written to the STP bit and the SLP bit concurrently, a transition to the time-base
timer mode or stop mode is performed.
• 0 is always read from this bit.
• This bit is only valid in the time-base timer mode or stop mode.
• When this bit is 0, the level of the external pin is held.
• When this bit is 1, the external pin is set to high impedance.
• This bit is initialized to 0 at a reset.
• When 0 is written to this bit, internal reset signals for 3 machine cycles is generated.
• When 1 is written to this bit, operation is not affected.
• 1 is always read from this bit.
• This bit specifies a transition to the timer or time-base timer mode.
• When 0 is written to this bit in the main-clock mode or PLL clock mode, a transition to
the time-base timer mode is performed.
When 0 is written to this bit is the sub-clock mode, a transition to the timer mode is
performed.
• This bit is initialized to 1 at a reset or an interrupt request issuance.
• 1 is always read from this bit.
• These bits set the CPU suspended clock cycle count in the CPU intermittent operation
function.
• Supply of the CPU clock is stopped for the specified cycle count by the instruction.
• The clock count can be selected from four types.
• This bit is initialized to 00
Note: Always writes 1 to this bit.
Function
at a reset.
B
5-8