Appendix A I/O Map; Table A-1 I/O Map - Fujitsu F2MC-8L Series Hardware Manual

APPENDIX A I/O Map

APPENDIX A I/O Map
Table A lists the addresses of the registers used by the internal peripheral functions of
the MB89120/120A series.
I/O Map

Table A-1 I/O Map

Register
Address
name
00 PDR0
H
01 DDR0
H
02 PDR1
H
03 DDR1
H
04 PDR2
H
05
H
06
H
07 SYCC
H
08 STBC
H
09 WDTC
H
0A TBTC
H
0B WPCR
H
0C PDR3
H
0D DDR3
H
0E PDR4
H
0F BZCR
H
10
H
11
H
12 SCGC
H
13
H
14 RCR1
H
15 RCR2
H
304
Register description
Port 0 data register
Port 0 data direction register
Port 1 data register
Port 1 data direction register
Port 2 data register
(Vacancy)
System clock control register
Standby control register
Watchdog timer control register
Timebase timer control register
Watch prescaler control register
Port 3 data register
Port 3 data direction register
Port 4 data register
Buzzer register
(Vacancy)
Peripheral control clock register
(Vacancy)
Remote-controll control register 1*
Remote-controll control register 2*
Read/Write Initial value
R/W XXXXXXXX
W 00000000
R/W XXXXXXXX
W 00000000
R/W 00000000
XXXXXXXX
R/W XXXMM100
R/W 00010XXX
R/W 0XXXXXXX
R/W 00XXX000
R/W 00XXX000
R/W XXXXXXXX
W 00000000
R/W 11111111
R/W XXXXX000
XXXXXXXX
R/W XXXXXX00
XXXXXXXX
R/W 00000000
R/W 00000000
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B
B