Fujitsu F2MC-8L Series Hardware Manual page 32

Table 1.2-2 CPU and Peripheral Functions for MB89120/120A Series
Parameter
MB89121
Output-only ports (N-ch open-drain):
Output-only ports (CMOS):
Ports
General-purpose I/O ports (CMOS):)
Total:
Timebase 21 bits
timer Interrupt cycle: 1.95 ms, 7.80 ms, 62.42 ms, 998.64 ms in 4.2-MHz main clock mode
Watch-dog Reset generation cycle
timer
Two channels of 8-bit timer/counter operation (timer 1 and timer 2 in independent clock operation), or 16-bit timer/counter
8/16-bit
operation (operation clock cycle: 1.9 µs to 487.6 µs)
timer/
Event counter operation and rectangular output both available by external clock in the timer 1 or 16-bit timer/counter operation
counter
mode.
8 bits
Serial I/O LSB first/MSB first selectability
One clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 1.9 µs, 7.6 µs, 30.5 µs)
Pe- Buzzer Output frequency
riph- output
eral
func-
3 independent channels (edge selection, interrupt vector, request flag, request output enable)
External
tions
Edge selectability (rising/falling/both)
interrupt 1
Used also for wake-up from stop/sleep mode. (Edge detection is also permitted in stop mode.)
External
interrupt 2
(wake-up)
Watch 15 bits
prescaler Interrupt cycle: 31.25 ms, 0.25 s, 0.50 s, 1.00 s in 32.768-kHz subclock mode
Remote-
control
transmissio
n frequency
generator
Peripheral Clock output cycle:
clock output
Note:
The clock cycle, conversion times, and other values not specifying the operation clock are for
4.2-MHz operation with the max. rate of main clock.
MB89123A MB89125A
Min. 998.6 ms in 4.2-MHz main clock mode
Min. 500 ms in 32.768-kHz subclock mode
1025Hz, 2051Hz, 4102Hz, 8203Hz in 4.2-MHz main clock mode
1024Hz, 2048Hz, 4096Hz in 32.768kHz subclock mode
Single 8-input channel (L-level interrupt and input
enable, independent of each other)
-
Also available for wake-up from stop/sleep mode.
(Level detection enabled even in sleep mode)
Internal 6-bit counter
The pulse width and cycle are program-selectable.
(Cycle: 0.48 to 1950 µs, "H" width: 0 t6o 1950 µs)
-
Also available as a 6-bit PPG
131.25 kHz, 175 kHz in 4.2-MHz main clock mode
16.38 kHz in 32.768-kHz subclock mode
1.2 MB89120/120A Series Product Lineup
Part number
MB89P133A MB89P131
4 (All also serve as peripherals.)
8
24 (All also serve as peripherals.
36
-
-
MB89P135A MB89PV130A
Single 8-input channel (L-level interrupt
and input enable, independent of each
other)
Also available for wake-up from stop/
sleep mode. (Level detection enabled
even in sleep mode)
Internal 6-bit counter
The pulse width and cycle are
program-selectable. (Cycle: 0.48 to
1950 µs, "H" width: 0 to 1950 µs)
Also available as a 6-bit PPG
5