Agilent Technologies X Series Manual page 592

Trigger
seconds. Thus, we could connect the even-second clock trigger to Ext1 and use then Ext1 as the sync
source for the periodic timer.
The figure below illustrates this third example. The top trace represents the even-second clock. It causes
the periodic timer to synchronize with the leading edge shown. The analyzer trigger occurs at a time
delayed by the accumulated offset from the period trigger event. The periodic timer continues to run, and
triggers continue to occur, with a periodicity determined by the analyzer time base. The timer output
(labeled "late event") will drift away from its ideal time due to imperfect matching between the time base
of the signal being measured and the time base of the analyzer, and also because of imperfect setting of
the period parameter. But the synchronization is restored on the next even-second clock event.
("Accumulated offset" is described in the in the Offset function section.)
Ext 1
Even-second Clock
Period
Timer
Trigger
Period
Sets the period of the internal periodic timer clock. For digital communications signals, this is usually set
to the frame period of your current input signal. In the case that sync source is not set to OFF, and the
external sync source rate is changed for some reason, the periodic timer is synchronized at the every
external synchronization pulse by resetting the internal state of the timer circuit.
Key Path
Remote Command
Example
Dependencies
Couplings
Preset
State Saved
Min
Max
592
Period
Accumulated Offset
Trigger, Periodic Timer
:TRIGger[:SEQuence]:FRAMe:PERiod <time>
:TRIGger[:SEQuence]:FRAMe:PERiod?
TRIG:FRAM:PER 100 ms
The invalid data indicator turns on when the period is changed, until the next
sweep/measurement completes.
The same period is used in the Gate Source selection of the period timer.
20 ms
GSM: 4.615383
Saved in instrument state
100.000 ns
559.0000 ms
Late Event
vsd45