Table 262. Buffer Modes Selection For Transmission/Reception - ST STM32L4 5 Series Reference Manual

Advanced arm-based 32-bit mcus

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Single Wire Protocol Master Interface (SWPMI)

Bit 2 RXMODE: Reception buffering mode

Note: This bit cannot be written while SWPACT bit is set.

Bit 1 TXDMA: Transmission DMA enable

Note: TXDMA is automatically cleared if the payload size of the transmitted frame is given as

Bit 0 RXDMA: Reception DMA enable

RXMODE/TXMODE

SWPMI Bitrate register (SWPMI_BRR)

Address offset: 0x04

Reset value: 0x0000 0001

Bits 31:6 Reserved, must be kept at reset value

Bits 5:0 BR[5:0]: Bitrate prescaler

This field must be programmed to set SWP bus bitrate, taking into account the F

programmed in the RCC (Reset and Clock Control), according to the following formula:

Note: The programmed bitrate must stay within the following range: from 100 kbit/s up to

This bit is used to choose the reception buffering mode. This bit is relevant only when

TXDMA bit is set (refer to

0: SWPMI is configured in Single software buffer mode for reception

1: SWPMI is configured in Multi software buffer mode for reception.

This bit is used to enable the DMA mode in transmission

0: DMA is disabled for transmission

1: DMA is enabled for transmission

0x00 (in the least significant byte of TDR for the first word of a frame). TXDMA is also

automatically cleared on underrun events (when TXUNRF flag is set in the SWP_ISR

This bit is used to enable the DMA mode in reception

0: DMA is disabled for reception

1: DMA is enabled for reception